1. Field of the Invention
The present invention relates to a testing system for a memory, and more particularly, to a testing system capable of detecting different kinds of faults for a memory under Input/Output compression (I/O compression).
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 is a diagram illustrating a conventional memory module 100 during the writing phase of the testing operation under I/O compression. As shown in FIG. 1, the memory module 100 comprises a testing system 110 and a DRAM 120. The memory module 100 comprises module data ends DE0, DE1, DE2 and DE3, and a module address end AE; similarly, the DRAM 120 comprises the memory data ends Dl0, Dl1, Dl2 and Dl3 corresponding to the module data ends DE0, DE1, DE2 and DE3, and a memory address end Al corresponding to the module address end AE. The memory module 100 inputs an address to the module address end AE for accessing data from the DRAM 120 through the module data ends DE0, DE1, DE2 and DE3. During the writing phase of the testing operation under the I/O compression, the testing system 110 couples the memory data ends Dl0, Dl1, Dl2 and Dl3 together, then writes the testing data TD and the testing address RA to the module data end DEO and the module address end AE respectively. As a result, the testing data TD can be written into the memory cells corresponding to the testing address RA and the memory data ends Dl0, Dl1, Dl2 and Dl3 in the DRAM 120, consequently reducing the time required by the testing system 110 writing the testing data TD. Furthermore, the testing address RA may be a row address and the module data end DEO is utilized as an input/output end during the writing phase of the testing operation under I/O compression.
Please refer to FIG. 2. FIG. 2 is a diagram illustrating the conventional memory module 100 during the reading phase of the testing operation under I/O compression. After the writing phase as shown in FIG. 1 is completed, the testing system 110 executes reading under the same I/O compression manner. In other words, the testing system 110 writes an identical testing address RA to the module address end AE, so the testing address RA is transmitted to the corresponding memory address end Ai of the DRAM 120. Therefore, the corresponding memory cells in the DRAM 120 output the data that was previously written through the memory data ends Dl0, Dl1, Dl2, and Dl3 to the data comparison circuit 130. The data comparison circuit 130 then compares the received data to determine the data consistency and accordingly outputs a reading determining data SDR to the module data end DEO. The reading determining data SDR may be logic “0”, “1”, or tri-state. The testing system 110 then determines if the memory cells corresponding to the address RA are damaged, according to the reading determining data SDR.
The advantage of the testing system 110 is that the testing is executed under I/O compression for a better testing speed and efficiency. The disadvantage, however, is that all the memory cells being accessed would carry identical data. In other words, when the testing data TD is written, identical data (i.e. data with the same data pattern) are written into the memory cells corresponding to the memory data ends D10, D11, D12 and D13. For instances, if the testing data TD is logic “1”, then the data written to the memory cell corresponding to the memory data ends D10, D11, D12 and D13 are [1111]; conversely if the testing data TD is logic “0”, then the data written to the memory cell corresponding to the memory data ends Dl0, Dl1, Dl2 and Dl3 are [0000]. Such tendency is likely to result in testing blind spot. Since the memory cell may be damaged in various ways, for instances, stuck-at fault, transition fault, coupling fault, and Neighborhood Pattern Sensitive Fault (NPSF) etc, writing identical data to all the memory cells being tested would cause inaccurate detection of the memory faults (i.e. how the memory is damaged), consequently decreasing the accuracy of the testing system 110 and causing inconvenience.